1. Field of the Invention
Embodiments of the present invention relate generally to computer architecture and, more specifically, to an approach to predictive verification of write integrity in a memory driver.
2. Description of the Related Art
In computer systems, generally, and in graphics processing units (GPUs), in particular, there is widespread utilization of static random access memory (SRAM) circuits. A conventional SRAM cell consists of two inverters connected front to back. Specifically, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input the first inverter. The output of one inverter represents a data bit, while the output of the complementary inverter represents the inverse of the data bit. To change the logic state (i.e. write a new value to the SRAM cell), a memory driver circuit overdrives one of the outputs to the opposite state. The overdrive action causes the driven inverter to change state, and the complementary inverter subsequently changes state to achieve the opposite logic state of both inverters.
Each inverter includes a pair of field effect transistors (FETs). One P-channel FET (PFET) is connected to a supply voltage, and one N-channel FET (NFET) is connected to ground. The mid-points of both FETs are connected together. This arrangement is termed a complementary-metal-oxide-semiconductor (CMOS) circuit. The high level is derived from the upper PFET that connects the supply voltage to the output while the lower NFET is gated off. In conventional systems, changing the state of the stored data is accomplished by driving the output of the inverter that is at the high level to the low level. In order to drive the output of the inverter to ground, the memory driver overpowers the upper PFET of the CMOS pair that forms the inverter. Therefore, the write driver that overdrives the inverter must be strong enough to pull the high level output below the NFET threshold of the driven inverter, even though the P-channel device is trying to pull the output up. The strength, or current sinking capacity, of an integrated FET is proportional to the area of the device. Hence, NFETs with the capability to overdrive an integrated PFET must have proportionally large area.
The NFETs applied in memory driver circuits are designed to have adequate capability to overdrive the inverters in the memory cells. In the actual circuits, a number of factors may conspire to cause a memory write operation to fail due to inability to achieve the necessary overdrive. These factors include process variations, temperature effects, degradation of supply voltage level, and aging effects. Thus, consideration of write failures is an important aspect of design with respect to system performance and reliability.
Assist circuits may be employed to help to minimize the possibility of write failures. In one instance of an assist circuit, the local supply voltage to the SRAM cell is driven to a lower level than the system supply voltage. This creates a larger margin for the driver, reducing the likelihood of failure. In another instance of an assist circuit, one of the bit-line voltages to the SRAM cell is driven to below ground as opposed to ground level. This again creates a larger margin for the driver, and again reduces the likelihood of failure.
One drawback associated with assist circuits is that such circuits incur an energy-per-access overhead. Further, in typical implementations, assist circuits are in continuous use. Finally, failures are detected only after occurring in active memory cells. That is, actual system failure must occur before corrective action can be implemented. If the system includes error correction capability, the system activates correction upon detection of errors. This incurs additional system cycles and, so, degrades system performance.
As the foregoing illustrates, what is needed in the art is a more effective technique for reducing the occurrence of SRAM write failures.